In the fabrication of semiconductor devices, contact holes and other features that are formed on a substrate are filled with a conductive material to provide contacts and other circuitry. One method for forming vertical and horizontal interconnects is by a damascene or dual damascene method. FIG. 1 illustrates a portion of a substrate 10 (e.g., wafer or microelectronic substrate) having conductive elements formed according to a prior art damascene method. The substrate 10 includes an insulating layer 12 (e.g., an interdielectric layer or ILD) deposited onto the substrate 10 and pattern etched to form interconnect openings 14. A barrier material layer 16, for example, tantalum (Ta), is deposited within the openings 14 to prevent diffusion of a conductive material such as copper into the insulating layer 12. Depending upon the material selected for the conductive layer, a separate seed layer 18, such as a copper seed layer, can then be deposited onto the barrier layer 16 prior to the formation of the metal layer, for example, by physical vapor deposition (PVD). The openings 14 can then be filled with a conductive metal 20 such as copper (Cu), resulting in excess material being deposited over the surface 22 of the substrate 10 outside or external to the openings 14.
In a typical process, excess deposited material 16, 20 external to the openings 14 is removed through planarizing or polishing the surface 22 of the substrate 10, for example, by a chemical-mechanical planarization (CMP) process, to isolate the conductive metal within the openings and produce a substrate 10 having an embedded conductive interconnect or other structure, as depicted in FIG. 1A. During CMP processes, a carrier holds and rotates the substrate in contact with a CMP pad and a polishing solution to mechanically remove material from the surface of the substrate. In an exemplary CMP process, excess copper material 20 is polished to the barrier layer 16 using a first slurry composition having a low abrasive content. The excess barrier layer 16 is then polished to the underlying insulating layer 12 using a second slurry composition.
Current low-k and future ultra low-k dielectrics are brittle and sensitive to the mechanical stresses needed to physically remove refractory metals, such as tantalum (Ta). Metal removal solutions that use ultra-low down forces are a current industry focus. Most barrier materials are difficult to remove by CMP because the barrier materials resist removal by abrasion and dissolution. Typical barrier removal slurries require a high abrasive concentration, which tend to result in dishing and scratching of the copper interconnect 20 within the openings 14 and detrimental erosion to the exposed insulating layer 12, including peeling and delaminating of low k dielectric layers from the wafer.
Another known approach for addressing those problems is to remove conductive materials using an electrochemical-mechanical polishing (ECMP) process or an electrolytic process. An exemplary ECMP process to remove the excess conductive material layer 20 and barrier layer 16 from substrate 10 is illustrated in FIG. 2. The substrate 10 (mounted on a substrate holder) is brought into contact with an electrolytic liquid 24 dispenses onto a processing pad 26 (situated on a platen). A current supply 28 is flowed through electrodes 29 to the electrolytic liquid 24 and the processing pad 26 is brought into contact with the substrate, resulting in the removal of the conductive material layer 20 and barrier layer 16 to provide a clean surface 22, as in FIG. 1A. An advantage of electrolytic and ECMP processes is that the downforce applied to a substrate by a processing pad during a CMP processing can be reduced or eliminated.
However, current ECMP and electrolytic processes for material removal have several drawbacks, including difficulties associated with hardware and design requirements (voltage supply, electrodes, etc.). Another drawback of electrolytic processing occurs at the end of the process as the metal (e.g., Ta) is almost completely cleared from a substrate layer (e.g., dielectric layer) and the electrolytic process is disrupted by the termination of electrical contact (i.e., open circuit), resulting in residual islands of conductive metal remaining on the substrate.
Therefore, it would be desirable to provide a process that overcomes such problems.